1. Technical Field
Exemplary embodiments of the present invention relate to a semiconductor integrated circuit system and a method of driving the same, and more particularly, to a semiconductor integrated circuit system and a method of driving the same capable of reducing disturbance of a phase-change memory device.
2. Related Art
Semiconductor devices may be divided into a volatile memory device and a nonvolatile memory device depending on whether to retain storage data in power off. The volatile memory device includes dynamic random access memories (DRAMs) and static random access memories (SRAMs). The nonvolatile memory device includes flash memories and electrically erasable programmable read only memories (EEPROMs).
The flash memories which are nonvolatile memories have been mainly used in various electronic appliances such as digital cameras, portable phones, and MP3 players.
However, the flash memory devices take a relatively long time to read data therefrom and write data therein and thus new semiconductor devices such as magnetic random access memories (MRAMs), ferroelectric random access memories (FRAMs), and phase-change random access memories (PRAMs) are being developed to replace the flash memory devices.
The PRAM which is one of the alternative devices uses a phase-change material in which mutual phase-changes are caused between a crystalline state and an amorphous state by heat, as a storage medium. As the phase-change material, a chalcogenide compound consisting of germanium (Ge), antimony (Sb) and tellurium (Te), that is, a GST material may be used.
Current may be supplied to the phase-change material as a source for supplying heat and amount of the supplied heat depends on intensity and a supplying time of the current. The phase-change material has a different resistance depending on a crystalline state thereof and thus logic information of the phase-change material is determined by a resistance difference.
In the phase-change memory device, all a plurality of memory cells connected to the same bit line are connected to one phase-change line. Thus, when a write current is applied to a specific memory cell, unintended phase-change may be caused in a memory cell adjacent to the specific memory cell. Such phenomenon is referred to as disturbance. The disturbance may become serious when a reset current having a relatively high level is applied, which will be described with reference to FIG. 1 in more detail.
Referring to FIG. 1, a phase-change line 10 connected to first and second word lines WL1 and WL2 is provided. A portion of the phase-change line 10 which is connected to the first word line WL1 is to be phase-changed into an amorphous state and a portion of the phase-change line 10 which is connected to the second word line WL2 has been previously phase-changed into an amorphous state. Here, a in reference numeral 20 is a heat electrode for supplying heat to the phase-change line 10.
When a reset current I is applied to make the portion of the phase-change line 10 electrically connected to the word line WL1 to be in an amorphous state, the portion of the phase-change line connected to the second word line WL2 is also affected by the reset current I.
Thus, the portion of the phase-change line 10 which is connected to the second word line WL2 may be phase-changed into a crystalline state again, thereby causing a read operation error.